Dr. Philippos Papaphilippou
Assistant Professor, Computer Science
Email papaphip@tcd.ie Phone https://philippos.infoBiography
Philippos Papaphilippou received his PhD from Imperial College London in 2021 and a master's from the University of Cambridge in 2017. His PhD was funded by dunnhumby (Tesco) for researching novel accelerators to improve the performance of big data analytics. He was a Microsoft contractor/intern and a senior CPU architect at Huawei Technologies R&D (UK) Limited. He has recently joined Trinity College Dublin, Ireland as an Assistant Professor for contributing to the Human Capital Initiative (HCI). His research topics include FPGAs, sorting algorithms, network switches, multi-processor architectures and data science.
Publications and Further Research Outputs
- Philippos Papaphilippou, Chris Brooks, Wayne Luk, An Adaptable High-Throughput FPGA Merge Sorter for Accelerating Database Analytics, 2020 30th International Conference on Field-Programmable Logic and Applications (FPL), 2020Journal Article, 2020, DOI
- Philippos Papaphilippou, Jiuxi Meng, Wayne Luk, High-Performance FPGA Network Switch Architecture, Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020Journal Article, 2020, DOI
- Philippos Papaphilippou, Holger Pirk, Wayne Luk, Accelerating the Merge Phase of Sort-Merge Join, 2019 29th International Conference on Field Programmable Logic and Applications (FPL), 2019Journal Article, 2019, DOI
- Philippos Papaphilippou, Paul H. J. Kelly, Wayne Luk, Pangloss: a novel Markov chain prefetcher, The Third Data Prefetching Championship (DPC3), held in conjunction with ISCA 2019, 2019Journal Article, 2019
- Philippos Papaphilippou and Jiuxi Meng and Nadeen Gebara and Wayne Luk, Hipernetch: High-Performance FPGA Network Switch, ACM Transactions on Reconfigurable Technology and Systems, 15, (1), 2021, p1--31Journal Article, 2021, DOI
- Stefan Krieg, Thomas Luu, Johann Ostmeyer, Philippos Papaphilippou, Carsten Urbach, Accelerating Hybrid Monte Carlo simulations of the Hubbard model on the hexagonal lattice, Computer Physics Communications, 236, 2019, p15--25Journal Article, 2019, DOI
- Philippos Papaphilippou, Wayne Luk, Accelerating Database Systems Using FPGAs: A Survey, 2018 28th International Conference on Field Programmable Logic and Applications (FPL), 2018Journal Article, 2018, DOI
- Philippos Papaphilippou, Chris Brooks, Wayne Luk, FLiMS: Fast Lightweight Merge Sorter, 2018 International Conference on Field-Programmable Technology (FPT), 2018Journal Article, 2018, DOI
- Philippos Papaphilippou and Wayne Luk and Chris Brooks, FLiMS: a Fast Lightweight 2-way Merger for Sorting, IEEE Transactions on Computers, 2022Journal Article, 2022, DOI
- Papaphilippou, Philippos, Sano, Kentaro, Adhi, Boma A., Luk, Wayne, Experimental survey of FPGA-based monolithic switches and a novel queue balancer, IEEE Transactions on Parallel and Distributed Systems, 2023Journal Article, 2023, DOI
- Papaphilippou, Philippos, Reconfigurable acceleration of big data analytics, Imperial College London, 2021Journal Article, 2021, DOI
- Philippos Papaphilippou and Kentaro Sano and Boma A. Adhi and Wayne Luk, Efficient Queue-Balancing Switch for FPGAs, 2021 International Conference on Field-Programmable Technology (ICFPT), 2021Journal Article, 2021, DOI
- Philippos Papaphilippou, Myrtle Shah, FPGA-extended General Purpose Computer Architecture, The 18th International Symposium on Applied Reconfigurable Computing (ARC), 2022Journal Article, 2022, DOI
- Philippos Papaphilippou and Paul H. J. Kelly and Wayne Luk, Demonstrating custom SIMD instruction development for a RISC-V softcore, 2021 31st International Conference on Field-Programmable Logic and Applications (FPL), 2021Journal Article, 2021, DOI
- Philippos Papaphilippou and Kelly Paul H. J. and Wayne Luk, Simodense: a RISC-V softcore optimised for exploring custom SIMD instructions, 2021 31st International Conference on Field-Programmable Logic and Applications (FPL), 2021Journal Article, 2021, DOI
- Philippos Papaphilippou, Paul H. J. Kelly, Wayne Luk, Extending the RISC-V ISA for exploring advanced reconfigurable SIMD instructions, Fifth Workshop on Computer Architecture Research with RISC-V (CARRV 2021), co-located with ISCA 2021, 2021Journal Article, 2021
- Philippos Papaphilippou,Zhiqiang Que, Wayne Luk, Efficiently Removing Sparsity for High-Throughput Stream Processing, The International Conference on Field-Programmable Technology (FPT) 2023, Yokohama, Japan, 2023, 2023Conference Paper, 2023, TARA - Full Text
- Philippos Papaphilippou, Thiem Van Chu, Efficient deadlock avoidance for 2D mesh NoCs that use OQ or VOQ routers, IEEE Transactions on Computers, 2024, p13Journal Article, 2024, TARA - Full Text